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    • 专利摘要:
    A method of producing a semiconductor device (10), comprising: a) providing a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being etched selectively with respect to the first layer, b) etching a part of the stack, a portion of the first layer forms a nanowire (132) disposed on the second layer, c) selective etching of the second layer, d) realization, under the nanowire, d a sacrificial portion having an etching selectivity greater than that of the second layer, e) producing a sacrificial gate and an external spacer (144) surrounding the sacrificial gate, f) etching the stack, revealing ends nanowire and sacrificial portion aligned with the outer spacer, g) selectively etching portions of the sacrificial portion from its ends forming aligned cavities under the outer spacer, h) performing an internal spacer (146) in the cavities.
    公开号:FR3060839A1
    申请号:FR1662530
    申请日:2016-12-15
    公开日:2018-06-22
    发明作者:Sylvain Barraud；Emmanuel Augendre；Remi COQUAND；Shay REBOH
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER OF ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment.
    Extension request (s)
    Agent (s): BREVALEX Limited liability company.
    METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH NANOWIRE AND ALIGNED EXTERNAL AND INTERNAL SPACERS.
    FR 3 060 839 - A1
    13/1 Method for producing a semiconductor device (10), comprising:
    a) production of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched with respect to the first layer,
    b) etching part of the stack, a portion of the first layer forms a nanowire (132) disposed on the second layer,
    c) selective etching of the second layer,
    d) production, under the nanowire, of a sacrificial portion having an etching selectivity greater than that of the second layer,
    e) making a sacrificial grid and an external spacer (144) surrounding the sacrificial grid,
    f) etching of the stack, revealing the ends of the nanowire and of the sacrificial portion aligned with the external spacer,
    g) selective etching of parts of the sacrificial portion, from its ends, forming cavities aligned under the external spacer,
    h) production of an internal spacer (146) in the cavities.

    i
    METHOD FOR PRODUCING A NANOWIRE SEMICONDUCTOR DEVICE AND
    ALIGNED EXTERNAL AND INTERNAL SPACERS
    DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The invention relates to a method for producing a semiconductor device with semiconductor nanowire (s) and comprising an internal spacer aligned with respect to an external spacer. The invention applies in particular to the production of multi-gate transistors, or multi-gate transistors, for example of the GAAFET type (“Gate-AII-Around Field-Effect Transistor”, or field effect transistor with a covering gate) . The invention applies in particular to the field of FET devices used for high performance and low consumption logic applications of microelectronics, as well as to that of the design and manufacture of FET transistors each comprising several nanowires superimposed one on the other. above others, used in the design of integrated circuits having improved electrical performance compared to the current state of the art.
    The invention advantageously applies to the production of one or more GAAFET transistors co-integrated, on the same substrate, with one or more FinFET transistors (“Fin Field Effect Transistor”, or field effect and fin transistor). .
    The document US 2008/0135949 A1 describes a process for producing an FET transistor, the channel of which is formed from several superimposed nanowires. In this method, a stack of semiconductor layers comprising an alternation of silicon layers and SiGe layers is first produced. When silicon is the material intended to form nanowires, a selective withdrawal of SiGe with respect to silicon is implemented at the channel region of the transistor so as to release the silicon nanowires before depositing the gate of the transistor around of these nanowires.
    With such a method, binding drawing rules must be applied in order to be able to release the silicon nanowires while maintaining the structure. Due to these design rules, the size of the semiconductor blocks forming the source and the drain is large and does not allow a high density of nanowires to be obtained. Furthermore, good positioning as well as good definition of the grid pattern is difficult to obtain.
    The documents US 8,679,902 B1 and EP 2,654,083 A1 describe other methods of producing transistors, the channels of which comprise superimposed nanowires and which are provided with a coating grid around the nanowires. In these documents, the grid is formed by a damascene-type process (approach known as “Gate-Last” or “Replacement Métal Gâte”, RMG), in which:
    a sacrificial grid is first formed by covering a stack of layers of silicon and of alternating layers of SiGe, at the level of the channel region, then
    - gate spacers and the source and drain regions are produced, then
    - the sacrificial grid is then etched through a masking layer covering the entire structure, this etching also serving to remove the SiGe (when the SiGe is used as sacrificial material and the channel is intended to be formed by silicon nanowires) at the channel region of the transistor to form the nanowires, and finally
    - The final grid is produced in the space formed by the etching of the sacrificial grid.
    The disadvantage of such an approach is that the etching implemented to remove the SiGe at the level of the channel region does not stop at the base of the opening formed in the masking layer for the removal of the sacrificial grid, this etching propagating towards the source and drain regions. During the selective withdrawal of SiGe with respect to silicon, there is no self-alignment of the SiGe removed with the location defined to form the grid. Consequently, the final grid deposited after the removal of these sacrificial layers is not self-aligned with the volume formed only by the removal of the sacrificial grid. This leads to an increase in stray capacitances within the transistor because during filling of the cavity with the gate materials, certain areas of the gate edge cover the source and drain areas.
    STATEMENT OF THE INVENTION
    An object of the present invention is to provide a method for producing a semiconductor device with semiconductor nanowire (s) allowing good alignment of the internal spacer with respect to the 'external spacer, which is suitable for the production of transistors with a high density on the support and which does not have the drawbacks of the methods of the prior art set out above.
    For this, the present invention provides a method for producing at least one semiconductor device, comprising at least the implementation of the following steps:
    a) production, on a support, of a stack of layers comprising at least a first layer of crystalline semiconductor and at least a second layer of crystalline semiconductor capable of being selectively etched with respect to the semiconductor of the first layer, the second layer being disposed between the first layer and the support;
    b) etching part of the stack of layers such that at least a portion of the first layer forms a nanowire disposed on a portion of the second layer;
    c) selective etching of said portion of the second layer;
    d) making, in at least one space formed under the nanowire by etching said portion of the second layer, of at least one portion of sacrificial material, the selectivity of etching of the sacrificial material with respect to the semiconductor of the first layer being greater than that of the semiconductor of the second layer with respect to the semiconductor of the first layer;
    e) making at least one sacrificial grid and at least one external spacer laterally surrounding the sacrificial grid;
    f) etching of the stack of layers, revealing the ends of the nanowire and of the portion of sacrificial material aligned with external lateral faces of the external spacer;
    g) selective etching of parts of the portion of sacrificial material, from the ends of the portion of sacrificial material, forming cavities aligned under the external spacer;
    h) production of at least one internal spacer in the cavities, aligned with the external spacer.
    Unlike the methods of the prior art in which the internal spacer is formed in cavities obtained by directly etching the initial stack of layers of crystalline semiconductors, the method according to the invention proposes to release the nanowire first and then to then deposit, at least under this nanowire, a sacrificial material having better selectivity of etching with respect to the semiconductor of the nanowire. Thus, unlike a method in which the locations of the internal spacer are defined by etching of SiGe selectively with respect to silicon (or vice versa), the etching implemented to form the locations of the internal spacer is much better controlled thanks to the use of the sacrificial material placed beforehand against or around the nanowire, thus improving the control of the thickness of material consumed by this etching. This allows the production of an internal spacer well aligned with the external spacer present above the nanowire, thus preventing the deposition of gate materials in regions for example intended for the production of source and drain.
    In addition, this method is well suited for producing on the same support several transistors with a high density (step, or “pitch” in English, of 40 nm or less, for example between about 30 nm and 40 nm).
    Advantageously, the sacrificial material can be semiconductor oxide, for example S1O2.
    The external spacer can advantageously include a dielectric material with a dielectric permittivity of less than or equal to 7. This makes it possible to reduce the stray capacitances and therefore to increase the operating speed of a CMOS circuit comprising transistors produced via the implementation of this process.
    The layers of the stack can be produced by epitaxy from a layer of semiconductor of the support.
    The semiconductor of the first layer can be silicon or SiGe, and the semiconductor of the second layer can be SiGe having a higher proportion of germanium than that of the semiconductor of the first layer. Alternatively, the semiconductor of the second layer can be silicon or SiGe, and the semiconductor of the first layer can be SiGe having a higher proportion of germanium than that of the semiconductor of the second layer.
    The semiconductor device may include at least one GAAFET type transistor, the channel of which is formed at least in part by the nanowire. This method advantageously applies to the production of GAAFET transistors advantageously having gate lengths of less than about 20 nm.
    In this case, the method can also include, between steps d) and e), a step of making insulation trenches around the nanowire and the portion of sacrificial material. The isolation trenches can be of the STI type (“Shallow Trench Isolation”, or shallow isolation trench). These trenches can in particular be made through part of the thickness of the support. The nanowire is thus produced before the insulation trenches (and not after as is usually the case), which makes it possible to conserve any constraint present in the nanowire, and facilitates obtaining a high density of nanowires.
    The method may also comprise, between steps a) and b), the production, on the support, of at least one portion of semiconductor of thickness substantially equal to that of the stack of layers, and the production isolation trenches may include the implementation of an etching also forming, in said portion of semiconductor, fins capable of forming the channel of a FinFET type transistor. The semiconductor portion of thickness substantially equal to that of the stack of layers can in this case form, with the support, a bulk-type substrate from which one or more FinFET transistors can be produced.
    Thus, a co-integration of one or more GAAFET transistors with one or more FinFET transistors is achieved. At least part of the steps used to produce the GAAFET transistor (s) can also be used to produce the FinFET transistor (s).
    The stack of layers can comprise several first layers stacked alternately with several second layers, and steps b) to h) can be implemented for all of the first and second layers. Thus, step b) of etching can form several superimposed nanowires spaced from each other by portions of the second layers.
    Step b) of etching can produce several portions of the first layer forming several nanowires arranged one next to the other, and steps c) to h) can be implemented for all of said nanowires.
    The support may correspond to a solid semiconductor substrate on which the stack of layers is produced. As a variant, the support may comprise a thick layer and a buried dielectric layer of a substrate of the semiconductor on insulator type, such as a surface layer of semiconductor of the substrate forms the second layer of the stack produced on the support.
    Step d) may include the implementation of a deposition of the sacrificial material around the nanowire. Thus, the process can then comprise, after the completion of the internal spacer, the production of a coating grid or at least partially coating around the nanowire.
    Etching step b) can be implemented using a hard mask produced on the stack by a SIT (“Sidewall Image Transfer”) or DSA (“Direct Self-Assembly”) type process, or by EUV lithography ("Extreme Ultra-Violet").
    The method can also comprise, after step h), the implementation of the following steps:
    - Realization of source and drain regions in contact with the ends of the nanowire;
    - removal of the sacrificial grid and of the portion of sacrificial material;
    - Producing a grid at locations formed by removing the sacrificial grid and the portion of sacrificial material, such that the grid at least partially surrounds the nanowire and such that the internal and external spacers surround the grid laterally.
    In this case, the source and drain regions can be produced by implementing a semiconductor epitaxy from a semiconductor of the support.
    The sacrificial grid and the grid can each comprise several distinct portions spaced from one another.
    This process is advantageously implemented for the manufacture of FET type transistors used for the production of integrated circuits for high performance logic applications and low electrical consumption, of NAND type Flash memories, of molecular memories, or for others. load sensor type applications. More generally, this method can be applied to the production of any structure requiring alignment of the grid between two or more semiconductor nanowires superimposed and spaced from each other.
    This method can be applied to the production of any type of semiconductor device requiring a good alignment of a grid with respect to one or more nanowires suspended above a support, or an alignment of an internal spacer with an external spacer.
    The term “nanowire” is used here to denote any portion of material of nanometric dimensions and of elongated shape, whatever the shape of the section of this portion. Thus, this term designates as many portions of elongated material of circular or substantially circular section, but also portions of material in the form of nano-beams or nano-bars comprising for example a rectangular or substantially rectangular section.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given for purely indicative and in no way limiting, with reference to the appended drawings in which:
    FIGS. 1A to 1Z represent the steps of a method for producing transistors with semiconductor nanowires, object of the present invention, according to a particular embodiment,
    - Figures 2A, 2B and 3A show steps of a method for producing transistors with semiconductor nanowires, object of the present invention, according to different alternative embodiments.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Reference is made to FIGS. 1A to 1Z which represent the steps of a method for producing a semiconductor device 10 comprising transistors 100 with semiconductor nanowires according to a particular embodiment. In this embodiment, the transistors 100 are of the GAAFET type. Furthermore, this method according to this particular embodiment also produces FinFET type transistors co-integrated with the transistors 100 on the same substrate within the semiconductor device 10.
    In FIG. 1A, the thicknesses of the various layers mentioned below correspond to the dimensions parallel to the axis Z shown in FIG. 1A.
    As shown in FIG. 1A, this method is implemented from a substrate of the semiconductor on insulator type, here SiGeOI (“SiGe-On-Insulator”, or SiGe on insulator) comprising a thick layer 102 of semi -conductor, for example silicon, on which is disposed a buried dielectric layer 104, or BOX ("Buried-Oxide"), comprising for example SiO2. The thickness of the buried dielectric layer 104 is for example equal to or greater than approximately 20 nm, and here equal to approximately 25 nm. The SiGeOI substrate also includes a surface layer 106 of semiconductor, here comprising SiGe. The thickness of the surface layer 106 is for example equal to approximately 8 nm, or between approximately 5 nm and 10 nm.
    Layers intended for the production of one or more nanowires of each of the transistors 100 are then produced on the substrate. In the embodiment described here, each transistor 100 is intended to include two superimposed or stacked silicon nanowires. For this, the layers produced on the substrate correspond to a layer of silicon 108 formed on the surface layer 106, a layer of SiGe 110 formed on the layer 108, and another layer of silicon 112 formed on the layer 110.
    The layers 106, 108, 110 and 112 together form a stack 113 of layers disposed on a support formed by the thick layer 102 and the buried dielectric layer 104. These layers 106, 108, 110 and 112 comprise crystalline semiconductors formed by epitaxy.
    The thickness of the second layer of SiGe 110 is for example equal to that of the surface layer 106 so that the distance between the nanowires of the transistors 100 (which will be formed from layers 108 and 112) corresponds to that between the dielectric layer buried 104 and the first nanowire. In addition, the thicknesses of the layers 108 and 112 correspond to the desired thicknesses of the nanowires of the transistors 100. The thicknesses of the layers 108 and 112 are for example equal to approximately 7 nm, and can be between approximately 2 nm and 50 nm.
    The number of layers of the stack 113 is chosen as a function of the number of superimposed nanowires that each transistor 100 is intended to have. For example, if each transistor 100 is intended to comprise three superimposed nanowires, then ίο the stack of layers 113 could comprise an additional SiGe layer placed on the layer 112 and an additional silicon layer placed on the additional SiGe layer.
    In general, each transistor 100 can comprise 1, 2, 3 or 4 superimposed nanowires (advantageously 3 nanowires), or even more than 4 superimposed nanowires, for example between approximately 1 and 20 superimposed nanowires.
    The materials of layers 108 and 112 are chosen as a function of the materials desired to form the nanowires of the transistors 100. In addition, the materials of layers 106 and 110 are chosen such that they can be etched selectively with respect to those of layers 108, 112. The materials used in this process for forming the nanowires as well as those of the layers between the nanowires may be different from the example Si / SiGe described here.
    In the embodiment described here, the layers 108, 110, 112 are produced in order to form, with the surface layer 106, a Si / SiGe superlattice of the type: Si / Sii-xGex / Si / Sii-xGex, with for example 0.05 <X <1.
    As a variant, it is possible that the nanowires are produced from a layer of SiGe and that layers of silicon form sacrificial layers interposed between the nanowires of SiGe.
    The stack 113 produced is then etched in order to keep only the parts of these layers at the level of regions intended for producing the transistors 100. For this, a layer 114, comprising for example TEOS or silicon nitride such as SiN, is deposited on the stack 113 (FIG. 1B), then etched so that the remaining part or parts of this layer 114 form a hard mask 116 covering the parts of the stack of layers 106 - 112 intended for producing the transistors 100. Lithography and etching steps are then implemented to remove the parts of the layers of the stack 113 as well as of the buried dielectric layer 104 located at the locations of the FinFET transistors. In FIG. 1C, the reference 118 designates the region or regions where the parts of the layers 104 - 112 have been omitted for the production of the FinFET transistors. The remaining part or parts of the buried dielectric layer 104 and of the stack 113 are intended for producing the transistors 100.
    An epitaxy is then implemented to form, in region 118, a portion 122 of semiconductor of the same kind as that of layer 102 (here silicon) and of thickness equal to the sum of that of the dielectric layer buried 104 and the remaining part of the stack 113. The hard mask 116 is then removed (FIG. 1D).
    A layer 124, intended to form a hard mask for producing the nanowires of the transistors 100, is then deposited on the stack 113 and on the portion 122 (FIG. 1E). The layer 124 comprises for example SiN and has for example a thickness of between a few nanometers (less than 10 nm) and a few tens of nanometers (less than 100 nm), for example equal to about 15 nm.
    One or more openings 126 are then made through the part or parts of the layer 124 which cover the part or parts 120 of the stack (FIG. 1F, on which a single opening 126 is made). This opening 126 is located opposite the part or parts of the stack 113 intended to be etched in order to form the nanowires of the transistors 100. The parts of the layer 124 present around the opening or openings 126 cover the parts of the stack to which the suspended nanowires will be anchored.
    In FIGS. 1F to 1K, only a part of the device 10 at the level of which nanowires of one of the transistors 100 are intended to be produced is shown. The view a) of each of FIGS. 1F to 1K represents a top view of this part of the device 10, and the views b) and c) correspond to section views respectively along the axes yy 'and xx' visible on the view at). The part of the layer 124 covering the portion 122 (not visible in FIGS. 1F to 1K) is preserved and is not etched so that the steps implemented described in connection with FIGS. 1F to 1K do not impact this part of the device 10 at which the FinFET transistors will be produced.
    A second hard mask is then formed in the opening 126 to etch the layers of the stack 113 and form the nanowires of the transistors 100. In FIG. IG, this second hard mask is produced from a layer 128, comprising by for example a metallic material such as TiN and a thickness for example equal to around 10 nm, which covers the layer 124 as well as the part of the stack 113 accessible through the opening 126.
    At this stage of the process, various steps can be implemented to etch the layers 106 - 112 and form the nanowires of the transistors 100.
    In the first embodiment described here, these steps correspond to those of a SIT type method. Portions of material, of slender shape and having their length (their largest dimension) extending parallel to the length of the nanowires intended to be produced, are formed on the part of the layer 128 located in the opening 126. The edges of these portions of material overflow on the part of layer 128 covering layer 124. Spacers 130 are then produced (deposition and anisotropic etching) around these portions of material, then these portions of material are removed in order to keep only the spacers 130. These spacers 130 are then used as a mask for etching the layer 128 which then serves to form the mask used for etching the stack 113. The structure obtained at this stage of the process is shown in FIG. 1H.
    The spacers 130 are then removed, then the parts of the stack 113 not covered by the remaining parts of the layers 124 and 128 are etched. The hard mask formed by the remaining parts of layer 128 is then removed (Figure 11).
    Selective etching of the SiGe of the layers 106 and 110 relative to the silicon of the layers 108 and 112 is then implemented, thus freeing the parts of the layers 108 and 112 lying opposite the opening 126 and which form the suspended nanowires 132 which will be used to form the channels of the transistors 100 (FIG. IJ). The nanowires 132 are anchored in the parts of the stack 113 covered by the parts of the layer 124.
    The SIT type steps described above for forming the nanowires 132 have the advantage of allowing the nanowires 132 to be produced with a high resolution or a high density. In fact, the spacers 130 formed around each of the initial material portions allow an etching mask to be produced, the resolution of which is doubled compared to the resolution with which these initial material portions are produced. Thus, by producing these portions of initial material with a resolution of approximately 80 nm (width, along the Y axis, of each of these portions equal to approximately 40 nm, and spacing, along the Y axis, between two neighboring portions (equal to approximately 40 nm), it is possible to produce nanowires 132 having a resolution of approximately 40 nm, that is to say a width (dimension along the Y axis) equal to approximately 20 nm and a spacing (along the Y axis) between two consecutive neighboring nanowires 132 equal to approximately 20 nm.
    As a variant, the steps used to produce the nanowires 132 previously described in connection with FIGS. 1H and 11 can be replaced by steps of a DSA type process in which blocks of copolymers are used as an etching mask, or stages of an EUV (“Extreme ultraviolet lithography”) etching process.
    The nanowires 132 are then encapsulated by depositing a sacrificial material 134, for example semiconductor oxide, in the free spaces formed around the nanowires 132 during the previous etchings implemented (FIG. 1K). This sacrificial material 134 is chosen such that its etching selectivity, that is to say the ratio between the etching speed of the sacrificial material 134 and that of the semiconductor of nanowires 132, is greater than that of the semiconductor of layers 106 and 110, and advantageously greater than or equal to about 100. For example, the sacrificial material 134 may correspond to oxide such as S1O2. A planarization, for example a CMP, of the sacrificial material 134, with stopping on the layer 124, is then implemented.
    In the figures IL to IP, the entire device 10, that is to say the parts in which the GAAFET and FinFET transistors are produced, is shown.
    Lithography and etching steps are then implemented to etch, around the region of the structure comprising the nanowires 132, STI-type isolation trenches 136 which are formed around the regions in which the transistors 100 are produced. These steps are also implemented so as to form, in the portion 122 and the solid layer 102, portions 138 of semiconductor intended to form the fins of the FinFET transistors (FIG. IM).
    The trenches 136 as well as the spaces formed between the portions 138 are then filled with a dielectric material 140, for example similar to the sacrificial material 134. A planarization, for example a CMP, with stop on the layer 124, is then implemented in order to remove the dielectric material 140 deposited outside the trenches 136 and the spaces between the portions 138 (FIG. IN).
    The layer 124 is then removed (FIG. 10).
    Anisotropic etching, dry or wet, is then implemented to remove part of the thickness of the dielectric material 140. This etching is stopped when the level of the dielectric material 140 reaches that of the buried dielectric layer 104 (FIG. IP). View b) of FIG. IP, which corresponds to a top view of the structure produced, makes it possible to see the regions where the nanowires 132 have been produced, as well as the parts of the stack 113 which have been preserved around the nanowires 132 and at which the source and drain regions of the transistors 100 are intended to be produced.
    Sacrificial grids 142, or dummy gates (“dummy gâte” in English) are then produced in particular on the stacks of nanowires 132 intended to form the channels of the transistors 100, as well as on the semiconductor portions 138 intended to form the channels. FinFET transistors (FIG. 1Q, in which views a) and b) are respectively a sectional view and a top view of the whole of the structure produced, and views c) and d) are sectional views respectively along the axes AA 'and BB' visible on view b)). These sacrificial grids 142 are for example formed from a stack of S1O2 and polysilicon.
    The sacrificial grids 142 are for example produced by implementing a conformal deposition (forming a layer of substantially constant thickness) of S1O 2 whose thickness is for example between approximately 2 nm and 6 nm, followed by a deposition of polysilicon forming a layer whose thickness is between approximately 50 nm and 200 nm. A CMP is then implemented, then a mask, for example made of silicon nitride and S1O2, of thickness for example equal to about 40 nm and whose pattern corresponds to that of the sacrificial grids 142, is then deposited on the polysilicon layer, then the layers of polysilicon and of S1O2 are then etched according to the pattern defined by the mask.
    An external spacer 144, comprising for example semiconductor nitride such as silicon nitride, or more generally a dielectric with low dielectric permittivity (less than or equal to 7, or “Low-k”), is then deposited and then etched anisotropically around each of the sacrificial grids 142 (FIG. IR).
    The parts of the stack 113 located at the level of the future source and drain regions of the transistors 100 are then etched, revealing the ends 141 of the nanowires 132 and the ends 143 of the portions of the sacrificial material 134 which are aligned with external lateral faces 145 of the external spacer 144 (Figure 1S).
    Parts of the sacrificial material 134 located around the nanowires 132 are then etched from the ends 143 revealed by the previous etching of the parts of the stack 113, consuming a thickness of sacrificial material 134 (dimension parallel to the Y axis) similar to the thickness of the external spacer 144. Because the selectivity of etching of the sacrificial material 134 relative to the semiconductor of the nanowires 132 is very important, precise control of the etched thickness of the parts of the sacrificial material 134 is possible . In addition, good etching uniformity for all of the parts of the sacrificial material 134 is also obtained thanks to this high etching selectivity. At the end of this etching, the lateral flanks of the remaining parts of the sacrificial material 134 located around the nanowires 132 are aligned with those of the sacrificial grids 142. The cavities formed by this etching, at the locations of the etched portions of sacrificial material 134, are then filled via a deposition of a dielectric material such as semiconductor nitride, for example SiN, or a Low-k dielectric, forming internal spacers 146 aligned vertically, as much at the outer faces (those being on the side of the source and drain regions) than internal faces (those located on the side of the grid), with the external spacer 144 (FIG. 1T). These steps forming the internal spacers 146 are not implemented for the FinFET transistors.
    A resumption of epitaxy is then implemented from the semiconductor regions which are no longer covered by the parts of the stack 113, forming source and drain regions 148 of the transistors 100 (FIG. 1U). This epitaxy also forms the source and drain regions of the FinFET transistors. The semiconductor formed by this epitaxy corresponds for example to silicon in the case of transistors 100 of the NMOS type, or of SiGe in the case of transistors 100 of the PMOS type. This epitaxy can be implemented such that the semiconductor formed generates a stress in the channel of the GAAFET transistors and / or the FinFET transistors.
    A dielectric layer 150, comprising for example semiconductor nitride such as SiN and having a thickness for example equal to about 40 nm, is then deposited on the entire structure. Another dielectric layer 152, comprising for example an oxide such as S1O2, then deposited then planarized with stop on the layer 150 (more precisely on the parts of the layer 150 located at the top of the sacrificial grids 142) (FIG. IV).
    The layer portions 150 placed at the top of the sacrificial grids 142 are then etched, for example by implementing a chemical etching of the H3PO4 type. The sacrificial grids 142 are then selectively etched with respect to the external 144 and internal spacers 146, by implementing for example a chemical etching of the TMAH type (FIG. 1W).
    The portions of sacrificial material 134 located around the nanowires 132 are then removed by etching. A gate dielectric (material with high dielectric permittivity, for example greater than around 3.9 or High-K, for example HfCL, ZrÜ2, T1O2, ΙΆΙ2Ο3, etc.) then at least one conductive gate material, for example metallic and advantageously corresponding to a TiN / W bilayer, are then deposited in the grid locations formed by the implementation of the previous steps of etching the sacrificial grids 142 and portions of sacrificial material 134, thus forming grids 154 of the GAAFET and FinFET transistors. The dielectric and conductive materials of the grids 154 surround each of the nanowires 132. Dielectric portions 156, comprising for example the same material as that of the layer 150, are then formed on the grids 154 (FIG. IX).
    The parts of the layers 150, 152 disposed on the source and drain regions 148 are removed so as to then form electrical contacts 158 on these regions 148 (FIG. 1Y).
    The GAAFET 100 and FinFET transistors are completed by depositing dielectric layers 160 on the entire structure and then forming, through these dielectric layers 160, connection pads 162 electrically connected to the gates 154 and to the electrical contacts 158 of the transistors ( Figure 1Z).
    In the particular embodiment described above, the substrate used to make the GAAFET 100 and FinFET transistors is a SiGeOI substrate. As a variant, the substrate used could be an SOI (“Silicon-On-Insulator” or silicon on insulator) substrate. The choice of the nature of the substrate depends in particular on the material intended to form the nanowires of the transistors 100.
    According to another variant, the substrate used to make the transistors 100 and 200 to be of the bulk or solid type, that is to say comprise only a solid layer of semiconductor, for example of silicon. FIG. 2A represents such a substrate 302, comprising for example silicon. In this case, the stack 113 of layers produced on such a substrate 302 at the start of the process can be such that it comprises a first layer of material 304 intended to be etched during the formation of the nanowires 132. For example, in the in the case of silicon nanowires 132, the first layer 304 may comprise SiGe. The thickness of this first layer 304 can also be greater than that of the other layers of the stack, for example of the order of 33 nm.
    The steps implemented to produce the transistors 100 and 200 from such a substrate 302 can be similar to those previously described in connection with Figures IB to 1Z. By way of illustration, FIG. 2B represents the structure obtained when the steps previously described in connection with FIGS. IA to 11 have been implemented. Then, when the nanowires 132 are released, the entire thickness of the parts of the layer 304 is eliminated.
    According to another variant, it is possible to use an SOI substrate and form a region 118 comprising a stack of layers allowing the formation of semiconductor nanowires. FIG. 3A represents the structure obtained after the implementation of the steps previously described in connection with FIGS. 1A-1C and in which, instead of then performing an epitaxy of silicon to form the portion 122, alternate epitaxies of SiGe and of silicon are used to produce an alternating stack of layers of SiGe (referenced 402 and 406 in FIG. 3A, the thickness of layer 402 being equal to the sum of the thicknesses of layers 104 and 106) and of silicon (referenced 404 and 408 in Figure 3A). Such a structure is advantageous when superimposed nanowires are integrated both on bulk substrate and on SOI substrate.
    In the particular embodiment described above, the method is implemented in order to produce co-integrated transistors 100 of GAAFET type and transistors of FinFET type. As a variant, this method can be implemented to form only GAAFET 100 transistors. In this case, the steps previously described in connection with FIGS. 1B to 1D can be omitted.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    1. Method for producing at least one semiconductor device (10), comprising at least the implementation of the following steps:
    a) production, on a support (102, 104, 302), of a stack (113) of layers (106 - 112, 304, 402 - 408) comprising at least a first layer (112) of crystalline semiconductor and at least a second layer (110) of crystalline semiconductor capable of being selectively etched with respect to the semiconductor of the first layer (112), the second layer (110) being disposed between the first layer (112) and the support (102, 104, 302);
    b) etching part of the stack (113) of layers such that at least a portion of the first layer (112) forms a nanowire (132) disposed on a portion of the second layer (110);
    c) selective etching of said portion of the second layer (110);
    d) making, in at least one space formed under the nanowire (132) by etching said portion of the second layer (110), of at least one portion of sacrificial material (134), the selectivity of etching of the sacrificial material (134) with respect to the semiconductor of the first layer (112) being greater than that of the semiconductor of the second layer (110) with respect to the semiconductor of the first layer (112);
    e) producing at least one sacrificial grid (142) and at least one external spacer (144) laterally surrounding the sacrificial grid (142);
    f) etching of the stack (113) of layers, revealing ends (141, 143) of the nanowire (132) and of the portion of sacrificial material (134) aligned with external lateral faces (145) of the external spacer (144 );
    g) selective etching of parts of the portion of sacrificial material (134), from the ends (143) of the portion of sacrificial material (134), forming cavities aligned under the external spacer (144);
    h) production of at least one internal spacer (146) in the cavities, aligned with the external spacer (144).
    [2" id="c-fr-0002]
    2. The method of claim 1, wherein the sacrificial material (134) is semiconductor oxide.
    [3" id="c-fr-0003]
    3. Method according to one of the preceding claims, in which:
    - the semiconductor of the first layer (112) is silicon or SiGe, and the semiconductor of the second layer (110) is SiGe comprising a proportion of germanium greater than that of the semiconductor of the first layer (112), or
    - the semiconductor of the second layer (110) is silicon or SiGe, and the semiconductor of the first layer (112) is of SiGe comprising a proportion of germanium greater than that of the semiconductor of the second layer (110).
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims, wherein the semiconductor device (10) comprises at least one GAAFET type transistor (100) whose channel is formed at least in part by the nanowire (132).
    [5" id="c-fr-0005]
    5. The method of claim 4, further comprising, between steps d) and e), a step of making insulation trenches (136) around the nanowire (132) and the portion of sacrificial material (134).
    [6" id="c-fr-0006]
    6. The method of claim 5, further comprising, between steps a) and b), producing, on the support (102,104, 302), at least one portion (122) of semiconductor of substantially thick equal to that of the stack (113) of layers, and in which the production of the insulation trenches (113) involves the implementation of an etching also forming, in said portion (122) of semiconductor, fins (138) capable of forming the channel of a FinFET type transistor.
    [7" id="c-fr-0007]
    7. Method according to one of the preceding claims, in which the stack (113) of layers comprises several first layers (108, 112) stacked alternately with several second layers (106, 110, 304), and in which the steps b) to h) are implemented for all of the first and second layers (106 - 112, 304).
    [8" id="c-fr-0008]
    8. Method according to one of the preceding claims, in which the etching step b) produces several portions of the first layer (112) forming several nanowires (132) arranged one next to the other, and in which the steps c ) to h) are used for all of said nanowires (132).
    [9" id="c-fr-0009]
    9. Method according to one of the preceding claims, in which:
    the support corresponds to a solid substrate (302) of semiconductor on which the stack (113) of layers (304,108,110,112) is produced, or
    - the support comprises a thick layer (102) and a buried dielectric layer (1044) of a substrate of semiconductor type on insulator, a surface layer (106) of semiconductor of the substrate forming the second layer of the stack (113) produced on the support.
    [10" id="c-fr-0010]
    10. Method according to one of the preceding claims, in which step d) comprises the implementation of a deposition of the sacrificial material (134) around the nanowire (132).
    [11" id="c-fr-0011]
    11. Method according to one of the preceding claims, in which the etching step b) is implemented using a hard mask (128) produced on the stack by a method of SIT or DSA type, or by EUV lithography.
    [12" id="c-fr-0012]
    12. Method according to one of the preceding claims, further comprising, after step h), the implementation of the following steps:
    - Realization of source and drain regions (148) in contact with the ends (141) of the nanowire (132);
    5 - removal of the sacrificial grid (142) and of the portion of sacrificial material (134);
    - Production of a grid (154) at locations formed by the removal of the sacrificial grid (142) and of the portion of sacrificial material (134), such that the grid (154) at least partially surrounds the nanowire (132) and such that
    10 internal and external spacers (144,146) laterally surround the grid (154).
    [13" id="c-fr-0013]
    13. The method of claim 12, wherein the source and drain regions (148) are produced by the implementation of a semiconductor epitaxy from a semiconductor of the support (102, 302).
    [14" id="c-fr-0014]
    14. Method according to one of the preceding claims, in which the sacrificial grid (142) and the grid (154) each comprise several distinct portions spaced from one another.
    1/12
    112
    S.60460
    113 {®-> X y
    2/12
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    法律状态:
    2018-01-02| PLFP| Fee payment|Year of fee payment: 2 |
    2018-06-22| PLSC| Publication of the preliminary search report|Effective date: 20180622 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 4 |
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    2021-12-31| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1662530A|FR3060839B1|2016-12-15|2016-12-15|METHOD FOR PRODUCING A NANOFIL SEMICONDUCTOR DEVICE AND EXTERNAL AND INTERNAL SPACERS ALIGNED|
    FR1662530|2016-12-15|FR1662530A| FR3060839B1|2016-12-15|2016-12-15|METHOD FOR PRODUCING A NANOFIL SEMICONDUCTOR DEVICE AND EXTERNAL AND INTERNAL SPACERS ALIGNED|
    US15/837,298| US10217849B2|2016-12-15|2017-12-11|Method for making a semiconductor device with nanowire and aligned external and internal spacers|
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